1. Field of the Invention
The present invention is related to a circuit and a method for synchronizing the clock signals in the IC layout, and more particularly, to a circuit and a method for controlling all the memory elements involved in the same data-flow to receive the synchronized clock signals in the IC layout so as to avoid the setup time error and the hold time error.
2. Description of the Prior Art
The clock signals in a digital circuit are often assumed to be synchronized when the IC designer designs the digital circuit. However, when the designed digital circuit diagram is carried out through the IC layout process, the staff of computer assisted design (CAD) has to consider the duration that the clock signal passes by the path from the clock signal source through the clock tree to each element and the resistance of the path, for balancing the received clock signal of each element (that is, synchronizing the received clock signal of each element). In this way, when the staff of CAD designs the routing of the clock signals, the resistance and the duration corresponding to each path of the branches of the clock tree has to be designed to be similar enough for avoiding that the elements receives the unsynchronized clock signals to result in the data error because of the setup time error and the hold time error.
In the prior art, many methods can balance the branches of the clock tree, for example, the Steiner tree. According to the above-mentioned methods, all the branches of the clock tree are considered to balance for synchronizing the branches of the clock tree. However, the conventional methods has more cost of the routing and increasing the number of buffers.